Packaged semiconductor devices, such as memory chips and microprocessor chips, typically include a semiconductor device mounted to a substrate and encased in a protective covering. The device includes functional features, such as memory cells, processor circuits, and interconnecting circuitry. The device also typically includes bond pads electrically coupled to the functional features. The bond pads are coupled to pins or other types of terminals that extend outside the protective covering for connecting the semiconductor device to buses, circuits and/or other semiconductor devices.
One conventional approach to reducing the surface area occupied by packaged semiconductor devices in compact electronic products is to stack one packaged device on another packaged device having an identical configuration. For example, as shown in FIG. 1, a conventional semiconductor device assembly 10 includes two identical packaged devices 12 (shown as a upper packaged device 12a and a lower packaged device 12b) that are connected to each other and to a printed circuit board (PCB) 14 with solder balls 16. Each packaged device 12 can include a semiconductor die 18 mounted to a support PCB 20 and encased with an encapsulant 22. Each die 18 has die bond pads (not shown) connected with corresponding bond pads 24a of the support PCB 20 with circuitry internal to the support PCB 20. The solder balls 16 connect the bond pads 24a of the upper package 12a to the bond pads 24b of the lower package 12b. Additional solder balls 16 connect the lower package 12b to corresponding bond pads 24b of the PCB 14.
One drawback with the conventional arrangement of FIG. 1 is that the bond pads 24a and 24b contribute to the overall footprint of the assembly 10. In particular, the bond pads 24a and 24b occupy a portion 26 of the perimeter of the PCB 14 and the support PCB 20. Accordingly, there remains a need for improved semiconductor device assemblies that occupy less surface area.